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VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
Features
* 2.488Gb/s 1:16 Demultiplexer * Targeted for SONET OC-48 / SDH STM-16 Applications * Supports FEC rates up to 2.7Gb/s
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
* Differential LVPECL Low Speed Interface * Single +3.3V Supply * 128 Pin 14x20mm PQFP Package
General Description
The VSC8164 is a 1:16 demultiplexer for use in SONET/SDH systems operating at a standard 2.488Gb/s data rate or forward error correction (FEC) data rate up to 2.7Gb/s. The device operates using a single 3.3V power supply, and is packaged in a thermally enhanced plastic package. The thermal performance of the 128PQFP allows the use of the VSC8164 without a heat sink under most thermal conditions.
VSC8164 Block DIagram
D0+ D0-
Output Register
DI+ DIHSCLKI+ HSCLKIDivide by 16 Divide by 2
D15+ D15CLK16O+ CLK16OCLK32O+ CLK32O-
Functional Description
Low Speed Interface The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D[15:0] with accompanying differential LVPECL divide by 16 clock CLK16O and divide by 32 clock CLK32O. The low speed LVPECL output drivers are designed to drive a 50 transmission line. The transmission line can be DC terminated with a split end termination scheme (see Figure 1), or DC terminated by 50 to VCC-2V on each line (see Figure 2). At any time, the equivalent split-end termination technique can be substituted for the traditional 50 to VCC-2V on each line. AC coupling can be achieved by a number of methods. Figure 3 illustrates an AC coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the downstream device were to have internal termination, the line to line 100 resistor may not be necessary. The divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Figure 1: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs VCC
VSC8164
R1 Zo
R1
downstream
Zo
R1||R2 = Zo , R1 = 125 R2 = 83
R2 VEE
R2
VCCR2 + VEER1 R1+R2 = VTerm
Figure 2: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8164
downstream
Zo
R1 =50 VCC-2V
R1 =50 VCC-2V
Figure 3: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8164
Zo Zo 50 50
100nF
downstream
bias point generated internally
100nF
VCC-2V
Page 2
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
High Speed Interface The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high speed inputs DI and HSCLKI. The data and clock inputs are internally terminated by a center-tapped resistor network. For differential input DC coupling, the network is terminated to the appropriate termination voltage VTerm (pins HSDREF, HSCLKREF) providing a 50 to VTerm termination for both true and complement inputs. For differential input AC coupling, the network is terminated to VTerm via a blocking capacitor. In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude (VCMI, VIHSDC). For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either side of the differential gate. Figure 4: High Speed Serial Clock and Data Inputs Chip Boundary
VCC = 3.3V
ZO
CIN
50
CAC VTerm CIN ZO
50
VEE = 0V
CIN TYP = 100 nF CAC TYP = 100 nF Supplies This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be 3.3V.
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should also be placed in parallel with the 0.1F and 0.01F capacitors mentioned above. Recommended capacitors are low inductance ceramic SMT X7R devices. For the 0.1F capacitor, a 0603 package should be used. The 0.01F and 0.001F capacitors can be either 0603 or 0402 packages. For low frequency decoupling, 47F tantalum low inductance SMT caps should be sprinkled over the board's main +3.3V power supply and placed close to the C-L-C pi filter. If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.
AC Characteristics
Figure 5: AC Timing Waveforms
CLK16O+
Parallel data clock output tpdd
D(0...15)+
Parallel data outputs
VALID DATA (1)
VALID DATA (2)
CLK32O+
Parallel data clock output
tpd32
Figure 6: High Speed Input Timing
DI+
High speed differential serial data input
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12 D13D14 D15
HSCLKI+
High speed differential clock input
tdsu
tdh
Page 4
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b a b
Single Ended Swing
=
= a * Differential swing () is specified as | b - a | ( or | a - b | ), as is the single ended swing. Differential swing is specified as equal in magnitude to single ended swing.
Differential Swing
Table 1: AC Characteristics Parameters tpdd tpd32 tDR, tDF tCLKR, tCLKF CLK16OD Description Data valid from falling edge of CLK16O+ CLK32O transition from falling edge of CLK16O+ D[15:0]+/- rise and fall times CLK16O+/- rise and fall times CLK16O+/- duty cycle distortion DI+ setup time with respect to falling edge of HSCLKI+ DI+ hold time with respect to falling edge of HSCLKI+ HSCLKI+/- duty cycle distortion Min
0 0
Max
800 1.0 400 250
Units
ps. ns. ps ps % of clock cycle ps
Conditions
-- --
45
20% to 80% into 50 Ohm load. See Figure 7 20% to 80% into 50 Ohm load. See Figure 7 High speed clock input at 2.488GHz
55
tdsu tdh
100
--
75
--
ps % of clock cycle
HSCLKID
40
60
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Table 2: DC Characteristics (Over recommended operating conditions). Parameters VOH VOL
VOLVPECL VIHSAC VIHSDC VCMI
Preliminary Datasheet
VSC8164
Description PECL output high voltage PECL output low voltage Low speed output voltage differential peakto-peak swing. Serial input differential voltage AC coupled Serial input differential voltage DC coupled Serial input common mode voltage Supply voltage Power dissipation Supply Current
Min
VCC-1.02 VCC2.00 400
Typ -- -- -- -- --
Max
VCC-0.70 VCC-1.62
Units
V V
Conditions 50 Termination to VCC 2.0V, See Figure 7 50 Termination to VCC 2.0V, See Figure 7 AC Coupled AC Coupled, internally biased to (VCC+VEE)/2 DC coupled
1300
mV
200 200 VCC-1.5 3.14
-- --
VCC-0.5
mV mV V V W mA
VCC
PD IDD
--
.75 220
3.47 1.1 320
3.3V 5% Outputs open, VCC = 3.45V Outputs open, VCC = 3.45V
-- --
Figure 8: Parametric Measurement Information
PECL Rise and Fall Time
80% 20%
Parametric Test Load Circuit PECL Output Load
Z0 = 50
50 VCC-2.0V
Tr
Tf
Page 6
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
Absolute Maximum Ratings (1)
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Power Supply Voltage, (VCC)....................................................................................................... -0.5V to +3.8V DC Input Voltage (Differential inputs) .................................................................................. -0.5V to Vcc+0.5V Output Current (Differential Outputs)....................................................................................................+/-50mA Case Temperature Under Bias ...................................................................................................... -55o to +125oC Storage Temperature.................................................................................................................. -65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................1500V
Recommended Operating Conditions
Power Supply Voltage, (VCC)..............................................................................................................+3.3V+5% Operating Temperature Range .........................................................0oC Ambient to +85oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8164 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V.
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Package Pin Descriptions
Table 3: Pin Identification Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Name
NC NC
I/O
I I I I I I -
Level
voltage GND typ HS HS +3.3V typ GND typ GND typ +3.3V typ HS HS +3.3V typ voltage -
Description
No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected High speed data input termination voltage reference No connect, leave unconnected Negative power supply pins High jspeed data input, true High speed data input, complement Positive power supply pins Negative power supply pins Negative power supply pins Positive power supply pins High speed clock input, complement High speed clock input, true Positive power supply pins High speed clock input termination voltage reference No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected
NC
NC NC NC NC NC NC HSDREF NC
VEE
D+ DVCC
VEE VEE
VCC HSCLKHSCLK+ VCC HSCLKREF NC NC NC NC NC NC NC NC NC NC NC
Page 8
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Name
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC NC NC
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
I/O
O O O O O O -
Level
+3.3V typ GND typ LVPECL LVPECL +3.3V typ LVPECL LVPECL +3.3V typ +3.3V typ LVPECL LVPECL GND typ
Description
No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected Positive power supply pins No connect, leave unconnected No connect, leave unconnected Negative power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data No connect, leave unconnected Positive power supply pins No connect, leave unconnected Positive power supply pins Low speed differential parallel data Low speed differential parallel data Negative power supply pins
VEE
D15+ D15VCC D14+ D14NC VCC NC VCC D13+ D13-
VEE
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Pin 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Name
D12+ D12VCC D11+ D11VCC D10+ D10-
Preliminary Datasheet
VSC8164
I/O
O O O O O O O O O O O O O O O O O O O O O O O
Level
LVPECL LVPECL +3.3V typ LVPECL LVPECL +3.3V typ LVPECL LVPECL GND typ LVPECL LVPECL +3.3V typ LVPECL LVPECL +3.3V typ LVPECL LVPECL GND typ LVPECL LVPECL +3.3V typ LVPECL LVPECL +3.3V typ LVPECL LVPECL GND typ LVPECL LVPECL +3.3V typ LVPECL LVPECL +3.3V typ +3.3V typ LVPECL
Description
Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Negative power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Negative power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Negative power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Positive power supply pins Positive power supply pins No connect, leave unconnected Low speed differential parallel data
VEE
D9+ D9VCC D8+ D8VCC D7+ D7-
VEE
D6+ D6VCC D5+ D5VCC D4+ D4-
VEE
D3+ D3VCC D2+ D2VCC VCC NC D1+
Page 10
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Note:
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
I/O
O O O O O O O -
Name
D1VCC D0+ D0-
Level
LVPECL +3.3V typ LVPECL LVPECL GND typ LVPECL LVPECL +3.3V typ LVPECL LVPECL -
Description
Low speed differential parallel data Positive power supply pins Low speed differential parallel data Low speed differential parallel data Negative power supply pins Parallel clock output, complement Parallel clock output, true Positive power supply pins Divided parallel clock output, complement Divided parallel clock output, true No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected No connect, leave unconnected
VEE
CLK16OCLK16O+ VCC CLK32OCLK32O+ NC NC NC NC NC NC NC NC NC NC NC NC NC
No connect (NC) pins must be left unconnected, or floating. Connecting any of these pins to either the positive or negative power supply rails may cause improper operation or failure of the device; or in extreme cases, cause permanent damage to the device.
G52239-0, Rev. 3.3 5/17/00
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
128 PQFP Package Drawings
Package Information
PIN 128 PIN 1
PIN 102
Key
RAD. 2.92 .50 (2)
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A A1 A2
E1 E
D D1 E
EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK
2.54 .50
E1 L e b R R1
PIN 38 D1 D TOP VIEW 10 TYP.
PIN 64
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
0.17
MAX.
b
LEAD COPLANARITY
NOTES:
L
Package #: 101-322-5 Issue #: 2
Page 12
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Package Thermal Considerations
This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table
Table 4: Thermal Resistance Symbol
jc ca
Description
Thermal resistance from junction to case. Thermal resistance from case to ambient with no airflow, including conduction through the leads.
C/W
1.34
25.0
Thermal Resistance with Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature difference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 5: Thermal Resistance with Airflow Airflow
100 lfpm 200 lfpm 400 lfpm 600 lfpm
ca (oC/W)
21 18 16 14.5
Maximum Ambient Temperature without Heatsink The worst case ambient temperature without use of a heatsink is given by the equation:
T A ( MAX ) = T C ( MAX ) - P ( MAX ) CA
where:
CA Theta case to ambient at appropriate airflow A(MAX) Ambient Air temperature C(MAX) Case temperature (85oC for VSC8164) P(MAX) Power (1.1 W for VSC8164)
Page 13
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
The results of this calculation are listed below:
Table 6: Maximum Ambient Air Temperature without Heatsink Airflow
none 100 lfpm 200 lfpm 400 lfpm 600 lfpm Max Ambient Temp oC 58 62 65 67 69
Preliminary Datasheet
VSC8164
Note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow.
Page 14
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Ordering Information
The order number for this product is formed by a combination of the device number, and package type.
VSC8164
Device Type VSC8164: 2.488Gb/s to 2.7Gb/s 1:16 SONET/SDH Demux
QR
Package QR: 128PQFP, 14X20mm Body
Notice
This document contains information about a new product in the preproduction phase of development. The information contained in this document is based on initial product characterization. Vitesse reserves the right to alter specifications, features, capabilities, functions, manufacturing release dates, and even general availability of the product at any time. The reader is cautioned to confirm that this datasheet is current prior to using it for design.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 15
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Page 16
VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52239-0, Rev. 3.3 5/17/00

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